Shih-Hung Chen

Macronix Int. Co., Ltd., Hsinchu, Taiwan|c|

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Papers21 papers

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MEMORY DEVICE AND MANUFACTURING METHOD OF THE SAME

Yihsuan Hsiao,Yenhao Shih,Shihhung Chen,Hangting Lue

(2015)

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SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD OF THE SAME

Shihhung Chen,Hangting Lue,Kuangyeu Hsieh

(2015)

Bibtex

Integrated circuit pattern and method

Shihhung Chen,Hangting Lue

(2014)

Bibtex

Memory architecture of 3D array with improved uniformity of bit line capacitances

Chunhsiung Hung,Hangting Lue,Shihhung Chen

(2014)

Cited by9Bibtex

Integration of 3D stacked IC device with peripheral circuits

Hangting Lue,Yihsuan Hsiao,Shihhung Chen,Yenhao Shih

(2014)

Cited by3Bibtex

Mask Design With Optically Isolated Via and Proximity Correction Features

Chihchang Hsieh,Shihhung Chen,Hangting Lue

(2014)

Cited by2Bibtex

Damascene Word Line

Shihhung Chen,Yenhao Shih,Hangting Lue

(2013)

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MULTILAYER CONNECTION STRUCTURE

Shihhung Chen,Hangting Lue, Hongji Lee, Chincheng Yang

(2013)

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Method for making multilayer connection structure

Shihhung Chen,Hangting Lue, Hongji Lee, Chincheng Yang

(2013)

Cited by7Bibtex

Multilayer Connection Structure and Making Method

Shihhung Chen,Hangting Lue, Hongji Lee, Chincheng Yang

(2013)

Cited by7Bibtex

Memory device, manufacturing method and operating method of the same

Hangting Lue,Shihhung Chen

(2013)

Cited by28Bibtex

NAND FLASH WITH NON-TRAPPING SWITCH TRANSISTORS

Shihhung Chen,Hangting Lue,Yenhao Shih

(2013)

Cited by5Bibtex

Memory with Off-Chip Controller

Shihhung Chen,Hangting Lue, K Y Hsieh

(2012)

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Structure of ECC Spare Bits in 3D Memory

Shihhung Chen,Hangting Lue, Ijen Huang

(2012)

Cited by4Bibtex

Multiple Patterning Method

Shihhung Chen,Hangting Lue

(2012)

Bibtex

Design innovations to optimize the 3D stackable vertical gate (VG) NAND flash

Chunhsiung Hung,Hangting Lue, Shuonan Hung,Chihchang Hsieh,Kuopin Chang, Shihlin Huang, Tzung Shen Chen,Chihshen Chang, Wenwei Yeh,Yihsuan Hsiao,Chiehfang Chen,Yanru Chen

(2012)

Cited by9Bibtex

A highly pitch scalable 3D vertical gate (VG) NAND flash decoded by a novel self-aligned independently controlled double gate (IDG) string select transistor (SSL)

Chihping Chen,Hangting Lue,Kuopin Chang,Yihsuan Hsiao,Chihchang Hsieh,Shihhung Chen,Yenhao Shih,Kuangyeu Hsieh,Tahone Yang,Kuangchao Chen,Chihyuan Lu

(2012)

Cited by20Bibtex

Reduced Number of Masks for IC Device with Stacked Contact Levels

Shihhung Chen,Hangting Lue

(2012)

Cited by7Bibtex

Memory Architecture of 3D Array With Alternating Memory String Orientation and String Select Structures

Shihhung Chen,Hangting Lue

(2012)

Cited by25Bibtex

A highly scalable 8-layer Vertical Gate 3D NAND with split-page bit line layout and efficient binary-sum MiLC (Minimal Incremental Layer Cost) staircase contacts

Shihhung Chen, H Y Lue,Yenhao Shih,Chiehfang Chen,Tzuhsuan Hsu,Yanru Chen,Yihsuan Hsiao, Shihcheng Huang,Kuopin Chang,Chihchang Hsieh, Guanru Lee, Alfredtunghua Chuang

Electron Devices Meeting, pp.2.3.1-2.3.4, (2012)

Cited by23EIWOSBibtex

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Shih-Hung ChenBinding

Papers21 papers

Shih-Hung Chen