Soner Yaldiz

Dept . of Electrical and Computer Engineering;Carnegie Mellon University;Dept . of Electrical and Computer Engineering Carnegie Mellon University

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Bio

Soner Yaldiz has been with Intel Labs, Hillsboro, OR, since 2012. His research focuses on computer-aided design of electrical circuits and systems. Yaldiz has a BS from Sabanci University, Istanbul, Turkey (2004), an MS from Koc University, Istanbul, Turkey (2006), and a PhD from Carnegie Mellon University, Pittsburgh, PA (2012).

Research Interests

Papers共 36 篇Author StatisticsCo-AuthorSimilar Experts

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Constructive Place-and-Route for FinFET-Based Transistor Arrays in Analog Circuits under Nonlinear Gradients

Arvind K. Sharma,Meghna Madhusudan,Steven M. Burns,Soner Yaldiz,Parijat Mukherjee,Ramesh Harjani,Sachin S. Sapatnekar

IEEE transactions on computer-aided design of integrated circuits and systemspp.1-1, (2024)

Cited0Views0EIWOSBibtex

Analog Layout Automation On Advanced Process Technologies

Soner Yaldiz

ISPD '23: Proceedings of the 2023 International Symposium on Physical Designpp.103-103, (2023)

Cited0Views0EIBibtex

A Digital LDO in 22-Nm CMOS with a 4-B Self-Triggered Binary Search Windowed Flash ADC Featuring Analog Layout Generator Framework

Xiaosen Liu,Soner Yaldiz,Parijat Mukherjee,Steven Burns,Harish Krishnamurthy,Krishnan Ravichandran,Zakir Ahmed,Nachiket Desai,Nicolas Butzen,James Tschanz,Vivek De

IEEE solid-state circuits letters (2023): 101-104

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A Generalized Methodology for Well Island Generation and Well-tap Insertion in Analog/Mixed-signal Layouts

Ramprasath Srinivasa Gopalakrishnan,Meghna Madhusudan,Arvind K. Sharma,Jitesh Poojary,Soner Yaldiz,Ramesh Harjani,Steven M. Burns,Sachin S. Sapatnekar

ACM transactions on design automation of electronic systems（2023）

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Machine Learning for Analog Layout

Steven M. Burns,Hao Chen,Tonmoy Dhar,Ramesh Harjani,Jiang Hu,Nibedita Karmokar,Kishor Kunal,Yaguang Li,Yishuang Lin,Mingjie Liu,Meghna Madhusudan,Parijat Mukherjee,David Z. Pan,Jitesh Poojary,S. Ramprasath,Sachin S. Sapatnekar,Arvind K. Sharma,Wenbin Xu,Soner Yaldiz,Keren Zhu

Springer eBookspp.505-544, (2022)

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A Digital LDO in 22nm CMOS with a 4b Self-triggered Binary Search Windowed Flash ADC Featuring Automatic Analog Layout Generator Framework

Xiaosen Liu,Soner Yaldiz,Parijat Mukherjee,Steven Burns,Harish Krishnamurthy,Krishnan Ravichandran,Zakir Ahmed,Nachiket Desai,Nicolas Butzen,James Tschanz,Vivek De

2022 IEEE Asian Solid-State Circuits Conference (A-SSCC) (2022)

Cited3Views0EIWOSBibtex

A Charge Flow Formulation for Guiding Analog/Mixed-Signal Placement

Tonmoy Dhar,S. Ramprasath,Jitesh Poojary,Soner Yaldiz,Steven Burns,Ramesh Harjani,Sachin S. Sapatnekarl

2022 Design, Automation &amp Test in Europe Conference &amp Exhibition (DATE) (2022)

Cited2Views0EIWOSBibtex

Analog/Mixed-Signal Layout Optimization Using Optimal Well Taps

S. Ramprasath,Meghna Madhusudan,Arvind K. Sharma,Jitesh Poojary,Soner Yaldiz,Ramesh Harjani,Steven M. Burns,Sachin S. Sapatnekar

ACM International Symposium on Physical Design (2022)

Cited1Views0EIBibtex

Performance-Aware Common-Centroid Placement and Routing of Transistor Arrays in Analog Circuits

Arvind K. Sharma,Meghna Madhusudan,Steven M. Burns,Soner Yaldiz,Parijat Mukherjee,Ramesh Harjani,Sachin S. Sapatnekar

2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD)（2021）

Cited6Views0EIWOSBibtex

ALIGN: A System for Automating Analog Layout

Tonmoy Dhar,Kishor Kunal,Yaguang Li,Meghna Madhusudan,Jitesh Poojary,Arvind K. Sharma,Wenbin Xu,Steven M. Burns,Ramesh Harjani,Jiang Hu,Desmond A. Kirkpatrick,Parijat Mukherjee,Soner Yaldiz,Sachin S. Sapatnekar

IEEE design & test（2021）

Cited33Views0EIWOSBibtex

Author Statistics

#Papers: 36

#Citation: 592

H-Index: 14

G-Index: 24

Sociability: 5

Diversity: 2

Activity: 5

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