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Surendra Rawat

Electrical Engineering

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Extraction of Trap Parameters for High-Κ Gate Stacks

Surendra Rawat,Samares Kar

(2008)

Cited by1Bibtex

Modelling of Layers and Traps in High-Κ Gate Stacks and Energy Band and Equivalent Circuit Representations

Surendra Rawat,Samares Kar

(2008)

Cited by3Bibtex

Salient Features in the Capacitance Characteristics of Ultrathin High-K Devices

Surendra Rawat, Dharmendar Reddy,Samares Kar

(2006)

Cited by1Bibtex

Extraction of Trap Parameters for High-K Gate Dielectric Stacks

Surendra Rawat,Samares Kar

(2005)

Bibtex

Characterization of accumulation layer capacitance for extracting data on high-/spl kappa/ gate dielectrics

Samares Kar,Surendra Rawat,Shaloo Rakheja, Dharmendar Reddy

IEEE Transactions on Electron Devices, (2005)

Cited by26Bibtex

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