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Toshio Nakatani is an IBM Distinguished Engineer at IBM Research's Tokyo Research Laboratory, where he has led various advanced compiler projects, including the industry-leading IBM Java JIT compilers. His research interests include computer architectures, optimizing compilers, and algorithms for parallel computer systems. Nakatani has a Ph.D. in computer science from Princeton University. He was recognized as an ACM Distinguished Engineer in 2007 and named as an IBM Distinguished Engineer in 2000. He received an Industry Achievement Award from Information Processing Society of Japan (IPSJ) in 2005, an IBM Corporate Award in 2000, and an IBM Outstanding Technical Achivement Award (OTAA) in 1977. He received three best paper awards for his co-authored papers at JVM'02 in 2002, MICRO-23 in 1990, and MICRO-22 in 1989. He is currently an editorial board member of IEEE Micro. He was a program committee member of the 34th and 36th annual ACM SIGPLAN conference on Programming Language Design and Implementation (PLDI2013 and 2015), The 4th and 5th International Workshop on Adaptive Self-tuning Computing Systems (ADAPT2014 and 2015), 11th IFIP International Conference on Network and Parallel Computing (NPC 2014), the 1st and 2nd International Workshop on Adaptive Self-Tuning Computing Systems for the Exaflop Era (EXADAPT2011 and 2012), The first International Workshop on Performance Modeling and Analysis of Workload Optimized System (FastPath 2012), the 3rd, 4th, and 5th Annual International Systems and Storage Conference (SYSTOR2010, 2011, and 2012), the 23rd, 24th, and 27th International Conference on Supercomputing (ICS2009, 2010, 2013), International Symposium on Code Generation and Optimization (CGO2007), 2nd Workshop on Java for HPC in 2000, and the 25th annual IEEE/ACM International Symposium on Microarchitecture (MICRO-25) in 1992. He was a Program Co-chair of the 24th annual IEEE/ACM International Symposium on Microarchitecture (MICRO-24) in 1991. He has been a member of TC10 WG10.3, IFIP since 2004.
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