Temperature-Aware NBTI Modeling and the Impact of Standby Leakage Reduction Techniques on Circuit Performance Degradation
IEEE Transactions on Dependable and Secure Computing（2011）
摘要
As technology scales, Negative Bias Temperature Instability (NBTI), which causes temporal performance degradation in digital circuits by affecting PMOS threshold voltage, is emerging as one of the major circuit reliability concerns. In this paper, we first investigate the impact of NBTI on PMOS devices and propose a temporal performance degradation model that considers the temperature variation between active and standby mode. We then discuss the resemblance between NBTI and leakage mechanisms, and find out that the impact of input vector and internal node on leakage and NBTI is different; hence, leakage and NBTI should be optimized simultaneously. Based on this, we study the impact of standby leakage reduction techniques (including input vector control and sleep transistor insertion) on circuit performance degradation considering active and standby temperature differences. We demonstrate the potential mitigation of the circuit performance degradation by these techniques.
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关键词
vector control,circuit reliability,digital circuit,integrated circuit reliability,pmos devices,leakage reduction,pmos threshold voltage,temperature-aware nbti modeling,leakage currents,circuit performance degradation,digital circuits,sleep transistor insertion,leakage mechanism,standby leakage reduction technique,circuit performance degradation.,major circuit reliability concern,temperature-aware nbti,temporal performance degradation,standby leakage reduction techniques,temporal performance degradation model,negative bias temperature instability,negative bias temperature instability (nbti),pmos device,mosfet,standby mode,standby temperature difference,leakage current,logic gates,logic gate,integrated circuit,transistors,degradation,threshold voltage,stress
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