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Vertical interconnects squeezing in symmetric 3D mesh Network-on-Chip
ASP-DAC, pp.357-362, (2011)
EI WOS SCOPUS
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Three-dimensional (3D) integration and Network-on-Chip (NoC) are both proposed to tackle the on-chip interconnect scaling problems, and extensive research efforts have been devoted to the design challenges of combining both. Through-silicon via (TSV) is considered to be the most promising technology for 3D integration, however, TSV pads d...More
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