Soft Error Hardened Latch and Its Estimation Method

We propose soft error robust latches which have multi storage nodes and present their efficiencies. The key technology of the latch is a feedback loop circuit with a data node and four gates. We also discuss a method of soft error estimation in robust circuits in this paper. The soft error immunity of this feedback loop circuit is estimated by circuit simulations with two models. The soft error immunity of the latch is estimated by device simulation more accurately. By these precise simulations, the latch is proven to be highly tolerant to soft errors. In addition, the latch protects from not only retention data upset but also transient noise releasing. The latch provides high immunity against all soft error problems with a simple circuit. It is easy to apply the latch technique to various latches, such as single latches, scan latches, and flip-flops.