Soft Error Hardened Latch and Its Estimation Method
JAPANESE JOURNAL OF APPLIED PHYSICS, pp. 2736-2741, 2008.
We propose soft error robust latches which have multi storage nodes and present their efficiencies. The key technology of the latch is a feedback loop circuit with a data node and four gates. We also discuss a method of soft error estimation in robust circuits in this paper. The soft error immunity of this feedback loop circuit is estimat...More
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