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Design optimization for single-event upset robustness using simultaneous dual-VDD and sizing techniques
ICCAD, pp.204-209, (2006)
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An optimization algorithm for the design of combinational circuits that are robust to single-event upsets (SEUs) is described. A simple, highly accurate model for the SEU robustness of a logic gate is developed. This model -- in posynomial form -- is integrated with performance and power constraints into an optimization framework based on...More
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