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Representative Traces for Processor Models with Infinite Cache

HPCA, pp.62-62, (1996)

Cited by: 104|Views9
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Abstract

Performance evaluation of processor designs using dynamic instruction traces is a critical part of the iterative design process. The widening gap between the billions of instructions in such traces for benchmark programs and the throughput of timers performing the analysis in the tens of thousands of instructions per second has led to the...More

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