Design Considerations for PD/SOI SRAM: Impact of Gate Leakage and Threshold Voltage Variation

We present a critical study of the impact of gate tunneling currents on the yield of 65-nm partially depleted/silicon-on-insulator (PD/SOI) SRAM designs. A new gate leakage monitor structure is developed to obtain device-specific gate leakage characteristics of the SRAM cells. This allows us to explore the design space accurately with reliable process information at an early stage. By relying on s...