Automatic Synthesis and Optimization of Partially Specified Asynchronous Systems.

DAC(1999)

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摘要
A method for automating the synthesis of asynchronous control circuits from high level (CSP-like) and/or partial STG (involving only functionally critical events) specifications is presented. The method solves two key subtasks in this new, more flexible, design flow: handshake expansion, i.e. inserting reset events with maximum concurrency, and event reshuffling under interface and concurrency constraints, by means of concurrency reduction. In doing so, the algorithm optimizes the circuit both for size and performance. Experimental results show a significant increase in the solution space explored when compared to existing CSP-based or STG-based synthesis tools
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关键词
VLSI,asynchronous circuits,circuit optimisation,formal specification,high level synthesis,signal flow graphs,asynchronous control circuits,automatic optimization,automatic synthesis,concurrency constraints,concurrency reduction,design flow,event reshuffling,functionally critical events,handshake expansion,high level specifications,partial STG specifications,partially specified asynchronous systems,reset events,solution space,
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