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Instruction flow-based front-end throttling for power-aware high-performance processors

ISLPED, pp.16-21, (2001)

Cited: 88|Views27
EI

Abstract

We present a number of power-aware instruction front-end (fetch/decode) throttling methods for high-performance dynamically-scheduled superscalar processors. Our methods reduce power dissipation by selectively turning on and off instruction fetch and decode. Moreover, they have a negligible impact on performance as they deliver instructio...More

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