Power Optimization for SRAM and Its Scaling
IEEE Transactions on Electron Devices(2007)
摘要
With technology scaling, there is a strong demand for smaller cell size, higher speed, and lower power in SRAMs. In addition, there are severe constraints for reliable read-and-write operations in the presence of increasing random variations that significantly degrade the noise margin. To understand these tradeoffs clearly and find a power-delay optimal solution for scaled SRAM, sequential quadrat...
更多查看译文
关键词
CMOS memory circuits,nanotechnology,quadratic programming,scaling circuits,SRAM chips
AI 理解论文
溯源树
样例
生成溯源树,研究论文发展脉络