Evaluation Of 3dics And Fabrication Of Monolithic Interlayer Vias

A compact model for interconnect length in homogeneous 3DICs is presented. The new model accounts for lateral TSV size, which is often much larger than the gate pitch, leading to TSV-induced gate blockage and potentially affecting the wirelength distribution. The impact of TSV diameter on maximum wirelength and wiring power is investigated, and systems with smaller vias are found to have better properties. Accordingly, fabrication results for nanoscale monolithically integrated copper vias are presented to demonstrate the feasibility of developing 3D systems with dense vertical integration which do not suffer from TSV-induced gate blockage.