Thermal design guideline and new cooling solution for a three-dimensional (3D) chip stack.
3DIC（2013）
摘要
In ASET (Association of Super Advanced Electronics Technologies), the thermal resistances of three-dimensional (3D) chip stacks have been measured by using 3D stacked thermal test chips which are implemented with PN junction diodes for temperature sensors and diffused resistors for heating. The equivalent thermal conductivity of interconnection between stacked chips (SnAg + Cu post) and that of TSV (Through-Silicon-Via) have been derived through these measurements. We propose how to estimate the thermal resistances of various 3D chip stacks, by storing these experimental results. Also, how much heat generation of a 3D chip stack is allowed, is discussed. Further, as one of possible new cooling solutions for a 3D chip stack, cooling though a laminate (organic substrate) is considered, and the thermal resistance dependence of a laminate on the thermal via density is experimentally clarified. It is also investigated how the thermal via material and the resin (dielectric) material affect the laminate thermal resistance by simulation. It is then discussed how much additional heat generation is allowed by this cooling though a laminate.
更多查看译文
关键词
cooling,copper,integrated circuit design,integrated circuit interconnections,integrated circuit packaging,integrated circuit testing,silver alloys,temperature sensors,thermal conductivity,thermal resistance,three-dimensional integrated circuits,tin alloys,3D chip stack,3D stacked thermal test chips,PN junction diodes,SnAgCu,TSV,cooling,diffused resistors,equivalent thermal conductivity,heat generation,integrated circuit interconnections,laminate thermal resistance,temperature sensors,thermal design guideline,thermal via density,through silicon via,TSV (Through Silicon Via),cooling though a laminate,interconnetion,thermal resistance,three diemenstional (3D) chip stack
AI 理解论文
溯源树
样例
生成溯源树，研究论文发展脉络
Chat Paper
正在生成论文摘要