A Near-Threshold 480 MHz 78 µW All-Digital PLL With a Bootstrapped DCO
J. Solid-State Circuits（2013）
摘要
This paper presents a near-threshold low-power all-digital PLL (ADPLL). It includes a 9-bit bootstrapped DCO (BDCO) to reduce supply voltage and power consumption, a weighted thermometer-controlled resistor network (WTRN) to achieve high linearity, and a 4-bit sigma-delta modulator to improve the resolution through dithering. The ADPLL is fabricated in a 90 nm SPRVT low-K CMOS process with a core area of 0.057 mm2. The measured results demonstrate that the bootstrapped ring oscillator (BTRO) oscillates at 602 MHz under a supply of 0.5 V and consumes 49.1 μW. The ADPLL operates at 480 MHz (48 MHz) with a power consumption of 78 μW (2.4 μW) under a supply voltage of 0.5 V (0.25 V).
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关键词
bootstrapped dco,low-voltage,sigma-delta modulator,sigma-delta modulation,all-digital phase-locked loop (adpll),bootstrapped circuit,near-threshold low-power all-digital pll,power consumption,low-power,near-threshold circuit,digital phase locked loops,voltage 0.5 v,power 78 muw,energy-efficient design,low-power electronics,frequency 480 mhz,phase locked oscillators,size 90 nm,frequency 602 mhz,power 49.1 muw,bootstrapped digitally-controlled ring oscillator,cmos digital integrated circuits,supply voltage,word length 4 bit,sprvt low-k cmos process,all-digital phase-locked loop,weighted thermometer-controlled resistor network,bootstrap circuits,low power electronics,low voltage
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