A 75dB SNDR, 10MHz conversion bandwidth stage-shared 2-2 MASH ΔΣ modulator dissipating 9mW.

This paper presents a new stage-sharing technique in a discrete-time 2-2 MASH Delta Sigma ADC to reduce the modulator power consumption. The proposed technique shares all active blocks of the modulator second stage with its first stage. The 2-2 MASH modulator utilizes second-order Chain of Integrators with Weighted Feed-forward Summation (CIFF) and Cascade of Integrators with Distributed Feedback Branches (CIFB) architectures for the first and second stages, respectively. Using the proposed technique, the second integrator and the adder op-amps of the modulator first stage are shared with the first and second integrator op-amps of the second stage. Measurement results show that the modulator designed in a 0.13um CMOS technology achieves 75-dB SNDR over a 5MHz signal bandwidth with a clock frequency of 130MHz, while dissipating less than 9mW analog power.