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Capacitor-couple ESD protection circuit for deep-submicron low-voltage CMOS ASIC
IEEE Trans. VLSI Syst., no. 3 (1996): 307-321
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Capacitor-couple technique used to lower snapback-trigger voltage and to ensure uniform ESD current distribution in deep-submicron CMOS on-chip ESD protection circuit is proposed. The coupling capacitor is realized by a poly layer right under the wire-bonding metal pad without increasing extra layout area to the pad. A timing-original des...更多
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