Fast Isomorphism Testing For A Graph-Based Analog Circuit Synthesis Framework

DATE '12: Proceedings of the Conference on Design, Automation and Test in Europe(2012)

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摘要
This contribution presents a major improvement for our analog synthesis framework with an explorative characteristic. The presented approach in principle allows the synthesis of a wide range of circuits, without the limitation to specific circuit classes. Defined by a specification of up to 15 different performances, a fully sized, transistor level circuit is synthesized for a provided process technology. The presented work reduces the needed computational effort and thus drastically reduces the synthesis time, while adding new abstraction into the framework to provide an even wider range of synthesized circuits - demonstrated in experimental results.
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关键词
analogue integrated circuits,graph theory,integrated circuit design,integrated circuit testing,fast isomorphism testing,fully sized transistor level circuit synthesis,graph-based analog circuit synthesis framework,
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