A 40nm 1.0Mb pipeline 6T SRAM with variation-tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist

Chi-Shin Chang,Hao-I Yang,Wei-Nan Liao,Yi-Wei Lin,Nan-Chun Lien,Chien-Hen Chen,Ching-Te Chuang,Wei Hwang,Shyh-Jye Jou,Ming-Hsien Tu,Huan-Shun Huang,Yong-Jyun Hu,Paul-Sen Kan,Cheng-Yo Cheng,Wei-Chang Wang,Jian-Hao Wang,Kuen-Di Lee,Chia-Cheng Chen,Wei-Chiang Shih

ISCAS（2013）

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摘要

We present a 1.0Mb pipeline 6T SRAM in 40nm Low-Power CMOS technology. The design employs a variation-tolerant Step-Up Word-Line (SUWL) to improve the Read Static Noise Margin (RSNM) without compromising the Read performance and Write-ability. The Write-ability is further enhanced by an Adaptive Data-Aware Write-Assist (ADAWA) scheme. The 1.0Mb test chip operates from 1.5V to 0.7V, with operating frequency of 800MHz@1.2V and 25°C. The measured power consumption is 23.21mW (Active)/2.42mW (Leakage) at 1.2V, TT, 25°C; and 6.01mW (Active)/0.35mW (Leakage) at 0.7V, TT, 25°C.

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关键词

frequency 800 mhz,power 23.21 mw,temperature 25 degc,power 6.01 mw,size 40 nm,sram chips,voltage 1.5 v to 0.7 v,uhf integrated circuits,adawa scheme,rsnm,variation-tolerant step-up word-line,low-power cmos technology,pipeline 6t sram,adaptive data-aware write-assist scheme,bit rate 1.0 mbit/s,variation-tolerant suwl,read static noise margin,pipelines,cmos integrated circuits,monte carlo methods

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