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An instruction timing model of CPU performance

International Symposium on Computer Architecture, no. 7 (1998): 165-178

Cited: 66|Views35

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dl.acm.org dblp.uni-trier.de academic.microsoft.com

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data collectioncache memory

Abstract

A model of high-performance computers is derived from instruction timing formulas, with compensation for pipeline and cache memory effects. The model is used to predict the performance of the IBM 370/168 and the Amdahl 470 V/6 on specific programs,/and the results are verified by comparison with actual performance. Data collected about pr...More

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Bernard L. Peuto

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Leonard J. Shustek

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