A 5.2-Gb/s Low-Swing Voltage-Mode Transmitter With an AC-/DC-Coupled Equalizer and a Voltage Offset Generator

IEEE Transactions on Circuits and Systems I-regular Papers(2014)

引用 22|浏览18
暂无评分
摘要
This paper describes a voltage-mode transmitter with an AC-/DC-coupled equalizer. A dual-loop regulator controls the tap-weight coefficient for the DC-coupled equalizer while maintaining the output matching condition. An AC-coupling technique is employed to enhance the edge rate and reduce the burden of the DC-coupled equalizer. The transmitter also supports the ability to add a DC differential voltage offset into the output signal so that the voltage margin of the link can be measured. The transmitter was fabricated using a 0.13-um CMOS technology. When 240- mVPP, 5.2-Gb/s data are sent over 20-inch FR4 channels, the eye of the received data has a voltage margin of 60 mV and a peak-to-peak jitter of 40 ps. The proposed transmitter consumes 5.86 mW from a 1.2-V supply while operating at 5.2 Gb/s.
更多
查看译文
关键词
voltage-mode transmitter,cmos integrated circuits,tap-weight coefficient,dual-loop regulator,voltage 1.2 v,edge rate,low-swing voltage-mode transmitter,serial interfaces,voltage offset generation,power 5.86 mw,transmitters,voltage regulators,output matching condition,cmos technology,ac-coupled equalization,voltage offset generator,voltage 60 mv,bit rate 5.2 gbit/s,equalisers,dc differential voltage offset,size 20 inch,fr4 channels,serial link,tap-weight control,size 0.13 mum,voltage margin,ac-dc-coupled equalizer,voltage 240 mv,impedance matching
AI 理解论文
溯源树
样例
生成溯源树,研究论文发展脉络
Chat Paper
正在生成论文摘要