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Design and CAD Challenges in sub-90nm CMOS Technologies

Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, pp.129-129, (2003)

Cited: 70|Views27
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Abstract

This paper discusses design challenges of scaled CMOS circuits insub-90nm technologies for high-performance digital applications.To continue scaling of the CMOS devices deep into sub-90nm tech-nologies,fully depleted SOI, strained-Si on SiGe, FinFETs withdouble gate, and even further, three-dimensional circuits will be uti-lizedto design ...More

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