2GHz 2Mb 2T Gain-Cell Memory Macro with 128GB/s Bandwidth in a 65nm Logic Process

As silicon technology scales, the possibility of fabricating dense memories is of great interest, particularly if the solution has low to no additional process cost. We demonstrate a 2Mb 2T gain-cell macro with 128GB/s bandwidth, fast 2ns cycle time, operating at 2GHz in a native 65nm logic process. Fast read access and cycle times are critical in lookup applications such as tag RAMs in microprocessors where read queries are abundant. In such a scenario replacing SRAM with a denser fast memory is desired. The 2T fully pipelined gain-cell macro features non-destructive read, partial-write support and sustains 8-cycle successive access to the same memory bank. The macro is fabricated in a high-performance 65nm process featuring 1.2nm nitrided gate oxide, 35nm gate length, enhanced channel strain, NiSi silicide, 8 layers of Cu metal interconnect, and low-K ILD enabling data-buses from the memory banks to run as high as 2GHz. This technology has a 0.57 mum2 6T SRAM cell. All internal circuits of the macro operate with a logic-compatible nominal IV supply with the exception of wordline drivers.