Fine-Grain Dynamic Leakage Reduction

Previous work in leakage current reduction for digital circuits can be divided into two main categories: static design-time selection of slow, low-leakage transistors for non-critical paths and dynamic de- activation of fast leaky transistors on critical paths. Leakage power is dominated by critical paths, and hence dynamic deactivation of fast transistors could potentially yield large savings. We introduce methodologies for comparing fine-grain dynamic deactivation tech- niques that include the effects of deactivation energy and startup latencies, as well as long-term leakage current. Existing dynamic leakage reduction techniques, although they have low leakage cur- rent also have large deactivation energies and significant startup latencies. The large deactivation energies require long idle times to amortize their overhead, and large startup latencies impact per- formance, limiting the applicability of these techniques within an active microprocessor. We introduce new circuit techniques that have a low deactivation energy when transitioning a circuit block into a low leakage state from which it can be woken quickly. We show how these techniques can be applied at a fine grain within an active microprocessor, and how microarchitectural scheduling poli- cies can improve their performance. The first technique deactivates SRAM read paths within I-cache memories saving over 40% of idle circuit leakage energy and over 20% of total I-cache energy when using a 70 nm process. The second technique dynamically deacti- vates idle registers reducing idle circuit leakage energy by 41.1% and up to 12.4% of total regfile energy. The third technique dy- namically deactivates read ports within a multiported register file. Independent of the second technique, read port deactivation saves up to 98.5% of idle circuit leakage energy and 47.8% of total en- ergy.