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These results demonstrate that the benefits of all these different silicon innovations can be combined to extend and continue the complementary metal–oxide– semiconductor scaling and performance trends

Integrated nanoelectronics for the future.

NATURE MATERIALS, no. 11 (2007): 810.0-812

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摘要

Integrated electronics has come a long way since the invention of the transistor in 1947 and the fabrication of the first integrated circuit in 1958. Given feature sizes as small as a few nanometres, what will the future hold for integrated electronics? Gordon Moore's prediction made over 40 years ago, that the number of transistors in an...更多

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简介
  • Gordon Moore’s prediction made over 40 years ago, that the number of transistors in an integrated circuit would double roughly every 24 months, continues to be the guiding principle of the semiconductor and computing industries.
  • Intensive research is currently being carried out by both industry and academia on electronic materials other than silicon and their integration onto silicon wafers for future high-performance and energy-efficient very-large-scale integrated (VLSI) nanoelectronics applications beyond 2015.
  • In the 90-nm node, strained silicon technology was introduced to boost performance and improve the energy efficiency of the CMOS transistors.
重点内容
  • Gordon Moore’s prediction made over 40 years ago, that the number of transistors in an integrated circuit would double roughly every 24 months, continues to be the guiding principle of the semiconductor and computing industries
  • The combined benefits of the tri-gate complementary metal–oxide– semiconductor (CMOS) transistor architecture with strained-silicon channels, highK gate dielectric, metal-gate electrode, and dual epitaxially grown raised source–drains have been demonstrated, and the resulting CMOS transistors show excellent short-channel characteristics with high drive-current performance[9]. These results demonstrate that the benefits of all these different silicon innovations can be combined to extend and continue the CMOS scaling and performance trends
  • The recent successful implementation of high-K/metal-gate in the 45-nm silicon technology node will have positive impact on the progress of high-K research for III–V. Another challenge is the low hole mobility in III–V materials and the lack of a p-channel device strategy for the CMOS configuration, which is required for lowpower applications
  • Transistor-level innovations such as the high-K/metal-gate stacks and the fully depleted tri-gate CMOS transistors will mitigate many of the key scaling challenges facing the 6T static random access memory (SRAM), including leakage power management and cell instability
结果
  • Intel has successfully implemented high-K/metal-gate stacks in its 45-nm technology node, leading to a significant improvement in transistor performance and reduction in gate leakage.
  • A transition for the present planar structure to non-planar, three-dimensional structures such as the double-gate transistor[7] and the tri-gate transistor[8], as shown, will improve short-channel performance and enhance scalability.
  • The integration of novel electronic materials with silicon is required to further improve speed and energy-efficiency of the transistors.
  • Compared with the doublegate transistor structure the tri-gate transistor structure provides more raw drive current per device footprint, further improves short-channel performance and is more manufacturable.
  • The combined benefits of the tri-gate CMOS transistor architecture with strained-silicon channels, highK gate dielectric, metal-gate electrode, and dual epitaxially grown raised source–drains have been demonstrated, and the resulting CMOS transistors show excellent short-channel characteristics with high drive-current performance[9].
  • These materials, in general, have significantly higher intrinsic (p or n) mobility than silicon, and they have the potential for enabling future high-speed applications at very low power-supply voltages[14].
  • Another challenge is the low hole mobility in III–V materials and the lack of a p-channel device strategy for the CMOS configuration, which is required for lowpower applications.
结论
  • Transistor-level innovations such as the high-K/metal-gate stacks and the fully depleted tri-gate CMOS transistors will mitigate many of the key scaling challenges facing the 6T SRAM, including leakage power management and cell instability.
  • Innovations in both transistor architecture and new materials, for example non-planar low-leakage transistors and high-K-based storage capacitors, certainly will continue to drive the scaling of DRAM well beyond today’s 65-nm dimension.
  • The relentless forward march of science and technology in shrinking transistors and integrating more novel electronic materials on silicon to produce everhigher-performance and more energyefficient computational and memory devices will definitely continue for many years to come.
总结
  • Gordon Moore’s prediction made over 40 years ago, that the number of transistors in an integrated circuit would double roughly every 24 months, continues to be the guiding principle of the semiconductor and computing industries.
  • Intensive research is currently being carried out by both industry and academia on electronic materials other than silicon and their integration onto silicon wafers for future high-performance and energy-efficient very-large-scale integrated (VLSI) nanoelectronics applications beyond 2015.
  • In the 90-nm node, strained silicon technology was introduced to boost performance and improve the energy efficiency of the CMOS transistors.
  • Intel has successfully implemented high-K/metal-gate stacks in its 45-nm technology node, leading to a significant improvement in transistor performance and reduction in gate leakage.
  • A transition for the present planar structure to non-planar, three-dimensional structures such as the double-gate transistor[7] and the tri-gate transistor[8], as shown, will improve short-channel performance and enhance scalability.
  • The integration of novel electronic materials with silicon is required to further improve speed and energy-efficiency of the transistors.
  • Compared with the doublegate transistor structure the tri-gate transistor structure provides more raw drive current per device footprint, further improves short-channel performance and is more manufacturable.
  • The combined benefits of the tri-gate CMOS transistor architecture with strained-silicon channels, highK gate dielectric, metal-gate electrode, and dual epitaxially grown raised source–drains have been demonstrated, and the resulting CMOS transistors show excellent short-channel characteristics with high drive-current performance[9].
  • These materials, in general, have significantly higher intrinsic (p or n) mobility than silicon, and they have the potential for enabling future high-speed applications at very low power-supply voltages[14].
  • Another challenge is the low hole mobility in III–V materials and the lack of a p-channel device strategy for the CMOS configuration, which is required for lowpower applications.
  • Transistor-level innovations such as the high-K/metal-gate stacks and the fully depleted tri-gate CMOS transistors will mitigate many of the key scaling challenges facing the 6T SRAM, including leakage power management and cell instability.
  • Innovations in both transistor architecture and new materials, for example non-planar low-leakage transistors and high-K-based storage capacitors, certainly will continue to drive the scaling of DRAM well beyond today’s 65-nm dimension.
  • The relentless forward march of science and technology in shrinking transistors and integrating more novel electronic materials on silicon to produce everhigher-performance and more energyefficient computational and memory devices will definitely continue for many years to come.
引用论文
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