Register Locking in an Asynchronous Microprocessor

ICCD, pp.351-355, (1992)

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A high performance register bank is a central componentof a RISC processor. A novel register bank design hasbeen developed, as an integral part of a self-timed implementationof a commercial RISC microprocessor, toaddress the problem of register interlocking in an asynchronousmicropipelined execution unit.The challenge in an asynchronous ...更多

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