Evaluation and Optimization of Signal Processing Kernels on the TRIPS Architecture

Diminishing performance gains in conventional architectu res are driving modern architectures to exploit parallelism mo re effectively. Next-generation architectures hold promise in the Digital Signal Processing (DSP) arena where high performance and power efficiency are equally important. To better identify optimization techniques on these emerging new arc hitectures, we optimized and evaluated a suite of benchmarks representative of high performance DSP applications. Usin g these benchmarks, this paper analyzes the performance effects of several code optimizations on a next-generation ge neral purpose processor.