A Practical Asic Methodology For Flexible Clock Tree Synthesis With Routing Blockages

In this paper, we propose a practical ASIC methodology for flexible clock tree synthesis (CTS). The allowed flexibility for clock network leads us to be able to synthesize some complex clock networks which may contain clock driver, sequential components, buffers, inverters, gated components. Macro blockages are also allowed to be presented in clock routing area to make CTS more practical. With multiple timing constraints applied, our CTS method first introduces node clustering and buffering to construct an initial clock tree in a bottom-up fashion, pursuing the minimum clock skew with macro blockages eluded. Then tree node pulling Lip and buffer insertion may be used to further improve clock tree performances. Experiments of CTS program using this methodology show that our CTS method works very well for some complex clock networks with timing closure achieved.