A one-quadrant discrete-time cellular neural network CMOS chip for pixel-level snakes
2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS(2005)
摘要
This paper introduces a CMOS on-chip implementation intended for pixel-level snakes (PLS). The resultant architecture follows the SIMD paradigm. The B/W processing is executed on a discrete-time cellular neural network (DTCNN) array with a one-quadrant (1Q) model. The gray-scale processing is also run locally on a dedicated hardware. Electrical simulations on a proof-of-concept chip with a resolution of 9×9 pixels in a 0.18 micrometre CMOS technology process (ST Microelectronics) give some estimation of the figures of merit expected with the future chip measurements.
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关键词
cellular neural nets,image processing,neural chips,neural net architecture,parallel architectures,1Q model,B/W processing,DTCNN array,SIMD paradigm,ST Microelectronics,discrete-time cellular neural network,gray-scale processing,neural network CMOS chip,one-quadrant cellular neural network,pixel-level snakes
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