A 240-mW 2.1-GS/s 52-dB SNDR Pipeline ADC Using MDAC Equalization

J. Solid-State Circuits(2013)

Cited 34|Views52
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Abstract
This paper introduces multiplying digital-to-analog converter (MDAC) equalization, a digital correction technique for pipeline ADCs that corrects MDAC gain, settling, and other dynamic errors using successive digital FIR filters operating on sub-ADC output samples. This technique reduces the required MDAC residue amplifier (RA) bandwidth relative to the sampling frequency, thereby reducing ADC power. MDAC equalization is demonstrated in a 240-mW 2.1-GS/s ping-pong pipeline ADC in 40-nm CMOS where MDAC RA power is reduced from 175 to 53 mW by 70%. The ADC achieves 58 dB SNR and 52 dB SNDR.
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Key words
residue amplifier (ra),sndr pipeline adc,multiplying digital-to-analog converter (mdac),digital correction,analogue-digital conversion,sndr,sub-adc output samples,ping-pong pipeline adc power,amplifiers,digital correction technique,multiplying digital-to-analog converter equalization,size 40 nm,equalization,pipeline,mdac equalization,sampling frequency,mdac ra bandwidth,mdac residue amplifier bandwidth,analog-to-digital converter (adc),fir filters,cmos digital integrated circuits,mdac ra power,snr,power 240 mw,successive digital fir filters,cmos,digital-analogue conversion,pipeline processing,power 175 mw to 53 mw,mdac gain
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