(Bi,La)4Ti3O12 as a ferroelectric layer and SrTa2O6 as a buffer layer for metal-ferroelectric-metal-insulator-semiconductor field-effect transistor
JOURNAL OF THE CERAMIC SOCIETY OF JAPAN(2009)
摘要
The metal-ferroelectric-metal-insulator-semiconductor field-effect transistor (MFMIS-FET) using the (Bi,La)(4)Ti3O12 (BLT) as a ferroelectric and SrTa2O6 (STA) as a buffer layer is prepared. The Au/STA/Si structure shows about 1 nF/cm(2) of the accumulation capacitance value which is equivalent to about 6.2 nm of SiO2. The leakage current density is lower than 10(7) A/cm(2) under 5 V. The remanent polarization of the 420 mn-thick BLT film was 35.2 mu C/cm(2) at 450 kV/cm. The MFMIS-FET was fabricated with different area ratio (A(I)/A(F)) front 1 to 8. From the drain current-gate voltage characteristics at the drain voltage of 0.2 V, the memory window is only 0.5 V for the device with A(I)/A(F) = 1 but it is increased to 1.8 V as the A(I)/A(F) is increased to 8. For the A(I)/A(F) ratio of 8, the "on" state of the drain current of 1.12 x 10(-5) A rapidly drops after 10(5) s to 2 x 10(-6) A and the "off" state current increase front 10(-7) A to 10(-6) A after 10(5) s. The on/off current ratio decrease from 3 x 10(2) to 8. (C) 2009 The Ceramic Society of Japan. All rights reserved.
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关键词
MFMIS structure,(Bi,La)(4)Ti3O12,SrTa2O6,FeRAM,Retention time
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