Highly-Associative Caches for Low-Power Processors

In this paper, we restate the advantages of CAM-tag caches based on a new cache energy model extracted from circuit designs for aggressive low-power cache designs in a0 .25 m 2.5 V CMOS process. We show that CAM-tag caches have comparable access latency, but give lower hit energy and higher hit rates than RAM-tag set-associative caches at the expense of approximately 10% area over- head. Although direct-mapped caches have lower hit ener- gies and faster access, they suffer higher miss rates which result in much larger total memory access energy as well as reduced performance. Our results demonstrate that CAM- tag caches are fast and energy-efficient, and are well-suited for both high-performance and low-power designs.