IP Authoring and Integration for HW / SW Co-Design and Reuse-Lessons Learned

The development process within the electronics design chain is adjusting to requirements caused by the complexity of today’s and tomorrow’s System on Chip (SoC) designs. Design for re-use is becoming a standard practice, sets new requirements for next generation tools and is leading to organizational changes within companies. Since 1998, we have discussed design methodology and tool requirements that would allow designers to create IP-dominated (SOC) devices at the system level of abstraction. This paper will review lessons learned in applying the proposed techniques to real design problems in the context of platform-based design. Furthermore this paper will review different techniques for IP Authoring required for modern SoC design. Different models of computation have to be supported to cover simulation and implementation of control, data flow and continuous time processing. Furthermore this paper will outline different techniques for IP Integration, focusing on early interaction within the design chain, between IP Creators and Integrators. The paper will close with lessons learned from user experiences by analyzing and comparing different use models of IP authoring for re-use and IP integration at the system level. Besides the model requirements for representing the IP blocks themselves, different solutions for test bench authoring and re-usable verification environments will be shown as well.