System-level optimization and benchmarking for InAs nanowire based gate-all-around tunneling FETs

The ON/OFF current and input capacitance of InAs nanowire based gate-all-around (GAA) tunnel FETs are modeled. Based on the device- and system-level models, optimization has been done and comparison has been made between TFETs and CMOS devices under different constraints for both single- and multi-core processors. Several performance metr...More