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Exploiting symmetry in temporal logic model checking

Formal Methods in System Design - Special issue on symmetry in automatic verification, no. 1-2 (1996): 77-104

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In practice, finite state concurrent systems often exhibit considerable symmetry. We investigate techniques for reducing the complexity of temporal logic model checking in the presence of symmetry. In particular, we show that symmetry can frequently be used to reduce the size of the state space that must be explored during model checking....更多

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