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The virtual write queue: coordinating DRAM and last-level cache policies
Proceedings of the 40th Annual International Symposium on Computer Architecture, no. 3 (2010): 72-82
EI
摘要
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU's data needs, and are mostly oblivious to the main memory. In this paper, we demonstrate that the era of many-core architectures has created new main memory bottlenecks, and mandat...更多
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