A Low Energy Network-On-Chip Fabric For 3-D Multi-Core Architectures

Vivek S. Nandakumar, Malgorzata Marek-Sadowska

Emerging and Selected Topics in Circuits and Systems, IEEE Journal（2012）

引用 18|浏览7

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摘要

In this paper, we study the network-on-chip (NoC) implemented with new vertical slit field effect transistors (VeSFETs). The unique properties of VeSFET circuits allow for very efficient power saving techniques that are not possible in complementary metal-oxide-semiconductor-based homogeneous 3-D NoCs. We demonstrate that the proposed 3-D hybrid architecture shows significant improvements in all network parameters including latency, power, and energy consumption compared to other practical 3-D NoCs.

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关键词

Memory on logic,network-on-chip (NoC),vertical slit field effect transistor (VeSFET),vertical slit transistor based integrated circuits (VeSTICs),three-dimensional (3-D) integration,3-D multi-core processsor,3-D NoC

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