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Efficient and effective placement for very large circuits

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions, no. 3 (1995): 349-359

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We present a new approach to simulated annealing and a new hierarchical algorithm for row-based placement which has obtained the best results ever reported for a large set of MCNC benchmark circuits. Our results indicate that chip area reductions up to 15% are achieved compared with TimberWolfSC v6.0 [13], [14], [17]. Our new hierarchical...更多

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