Modeling the Response of Bang-Bang Digital PLLs to Phase Error Perturbations

Moataz Abdelfattah,Maged Ghoneima,Yehea I. Ismail,Amr Lotfy,Mohamed Abdel-moneum,Nasser A. Kurd,Greg Taylor

Proceedings of the IEEE Custom Integrated Circuits Conference（2012）

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摘要

Bang-Bang phase locked loops (BB-PLLs) offer a low power implementation of digital PLLs. However, the response of BB-PLLs, unlike linear PLLs, depends on the magnitude of the phase error, and thus, exhibits hard nonlinearity. This paper presents a generic modeling methodology for digital BB-PLLs in the locked state using simple time domain analysis. The proposed model predicts the response of BB-PLL to a given phase error magnitude in terms of stability (maintaining lock), and settling time (relock time). The model further aids the design process by providing insight for the system response in terms of the loop parameters. An example BB-PLL system is implemented in 32nm technology, and the proposed model is applied. Verified by analog-mixed signal (AMS) simulations, the model was successful in predicting the system response, and indicating stability and settling time of the system for a given phase error magnitude.

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关键词

digital phase locked loops,low-power electronics,perturbation techniques,stability,time-domain analysis,AMS simulations,BB-PLL system,analog-mixed signal simulations,bang-bang digital PLL,bang-bang phase locked loops,design process,digital BB-PLL,generic modeling methodology,linear PLL,locked state,loop parameters,low power implementation,phase error magnitude,phase error perturbations,settling time,stability,system response,time domain analysis

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