Test pattern generation for static burn-in based on equivalent fault model

2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013, (2013)

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Abstract:

To speed up the deterioration of a circuit under test (CUT), an input pattern is needed to maximize its leakage power in the static burn-in process. This paper presents an efficient pattern generation method with ATPG approach. To reduce the effort of precise power calculation, a metric that is linearly related to the leakage power of CUT...More

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