Buffer space planning for long interconnections based on corner block list

In order to reduce interconnect delays in circuits, we introduce a buffer space planning algorithm for non-monotone routes based on Corner Block List. After the heuristic floorplaner finds a floorplanning solution, the algorithm will check the interconnect delays and insert buffers for those cannot achieve time closures. The optimization objective is to minimize the impact on the floorplan. Assume the size of a buffer is b*b, we show that for the buffers connecting two points, the worst case may increase the size of the chip for 2b and b respectively in the two dimensions. And we prove this is the maximum size increase for one interconnect delay. The efficiency of our algorithm is showed by experimental results. © 2005 IEEE.