True Worst-Case Clock Skew Estimation Under Process Variations Using Affine Arithmetic

With the shrinking of IC feature size, clock skew uncertainty is introduced due to the presence of process variations, which significantly affects high-speed clock-tree performance. Affine arithmetic is adopted to capture both circuit topological correlation and process parameter spatial correlation. An affine arithmetic based method is proposed for true worst-case clock skew estimation. The proposed method is tested on circuit examples. We demonstrate the accuracy of the proposed method by comparing our results with Monte Carlo simulation.