Specific Design and Optimization of JTAG IP Core
Chengdu(2009)
摘要
A JTAG IP core based on IEEE1149.1 standard has been reported here, including its design and implementation. It has been described using synthesized Verilog HDL language. Simulation demonstration has also been made and the result has been synthesized. It has been demonstrated that the IP core design is feasibility. Moreover, based on the characteristic of DFT using JTAG standard, some improvements on the JTAG structure are proposed to get an optimized result.
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关键词
automatic testing,design for testability,hardware description languages,integrated circuit testing,DFT,IEEE1149.1,JTAG IP core,Verilog HDL language,
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