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The proposed trellis application specified instruction-set processor is evaluated with other trimode state-of-the-art decoders which reveals its high decoding efficiency

High-Throughput Trellis Processor for Multistandard FEC Decoding

VLSI) Systems, IEEE Transactions , no. 99 (2015): 1-2767

Cited: 9|Views40

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application-specific instruction-set processor (asip)forward--backward recursion (fbr)multistandard forward error correction (fec)single instruction multiple data (simd)trellis decoding.More(4+)

Abstract

Trellis codes, including Low-Density Parity-Check (LDPC), turbo, and convolutional code (CC), are widely adopted in advanced wireless standards to offer high-throughput forward error correction (FEC). Designing a multistandard FEC decoder is of great challenge. In this paper, a trellis application specified instruction-set processor (TASI...More

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Introduction

B ASEBAND computing platform for wireless communications needs to support multiple standards with limited power consumption and silicon area cost.
It prompts the research of the highly reusable modules.
Forward error correction (FEC) decoder is essential to improve the baseband performance and supply more reliability.
It is reported that approximately 40% of workload in baseband processing is for FEC decoding [1], [2], which equals to 10–100 GOPs/s within

Highlights

B ASEBAND computing platform for wireless communications needs to support multiple standards with limited power consumption and silicon area cost
forward error correction (FEC) decoder faces the situation of multiple algorithms coexisting due to its widely adoption in all 2G–4G wireless standards, including 3rd Generation Partnership Project (3GPP)-Long Term Evolution (LTE)(A), 802.11n, 802.16e, UMTS, CDMA, and GSM
It is reported that approximately 40% of workload in baseband processing is for FEC decoding [1], [2], which equals to 10–100 GOPs/s within
2) Logic Sharing Results: The silicon area reduction through trellis application specified instruction-set processor (TASIP) hardware sharing is discussed in the following
The data path and memory modules are shared by the decoding algorithms which leads to an area and memory bandwidth saving
The proposed TASIP is evaluated with other trimode state-of-the-art decoders which reveals its high decoding efficiency

Results

SYNTHESIS RESULTS AND COMPARISON

The proposed design is synthesized by Synopsys Design Compiler, placed and routed by Cadence Encounter.
The total power consumption is 322 mW with the clock frequency of 200 MHz. The authors first discuss on the saving of memory cost, 3GPP-LTE Turbo, 802.11n LDPC, 802.16e LDPC, and 802.11 CC are separately implemented to compare the resource consumption with this TASIP solution.
There are some modules shared, additional multiplexing routes are needed for the memory sharing and datapath sharing
In another aspect, it reveals an obvious register resources saving through the unified architecture.

Conclusion

A trellis processor architecture supporting high-throughput multistandard turbo, QC-LDPC, and

CC decoding is proposed.
A trellis processor architecture supporting high-throughput multistandard turbo, QC-LDPC, and.
CC decoding is proposed.
The decoding algorithm similarities are investigated and a parallel FBR decoding routine along with a code segmentation method is given.
Under the FBR characteristics, a unified SIMD architecture is proposed supporting FR and BR simultaneously processing.
The data path and memory modules are shared by the decoding algorithms which leads to an area and memory bandwidth saving.
The proposed TASIP is evaluated with other trimode state-of-the-art decoders which reveals its high decoding efficiency

Tables

Table1: FBR CONTROLLING KEY SIGNALS
Table2: LOGIC SHARING IN TERMS OF μm2 part of the core with the same distance to the permutation network. ATU routes in relatively less density to avoid routing congestion
Table3: FEC INSTRUCTIONS
Table4: SUMMATION OF MEMORY BANDWIDTH (BITS/CYCLE)
Table5: COMPARISON WITH STATE-OF-THE-ART MULTIMODE FEC DECODERS
Table6: MEMORY SHARING RESULTS IN TERMS OF BITS

Download tables as Excel

Funding

This work was supported by the National High-Tech Research and Development Program (863 Program) of China under Grant 2014AA01A705. (Corresponding author: Dake Liu.)

Reference

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Author

Zhenzhi Wu

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Dake Liu (刘大可)

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