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The proposed trellis application specified instruction-set processor is evaluated with other trimode state-of-the-art decoders which reveals its high decoding efficiency

High-Throughput Trellis Processor for Multistandard FEC Decoding

VLSI) Systems, IEEE Transactions  , no. 99 (2015): 1-2767

Cited: 9|Views40
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Abstract

Trellis codes, including Low-Density Parity-Check (LDPC), turbo, and convolutional code (CC), are widely adopted in advanced wireless standards to offer high-throughput forward error correction (FEC). Designing a multistandard FEC decoder is of great challenge. In this paper, a trellis application specified instruction-set processor (TASI...More

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Introduction
  • B ASEBAND computing platform for wireless communications needs to support multiple standards with limited power consumption and silicon area cost.
  • It prompts the research of the highly reusable modules.
  • Forward error correction (FEC) decoder is essential to improve the baseband performance and supply more reliability.
  • It is reported that approximately 40% of workload in baseband processing is for FEC decoding [1], [2], which equals to 10–100 GOPs/s within
Highlights
  • B ASEBAND computing platform for wireless communications needs to support multiple standards with limited power consumption and silicon area cost
  • forward error correction (FEC) decoder faces the situation of multiple algorithms coexisting due to its widely adoption in all 2G–4G wireless standards, including 3rd Generation Partnership Project (3GPP)-Long Term Evolution (LTE)(A), 802.11n, 802.16e, UMTS, CDMA, and GSM
  • It is reported that approximately 40% of workload in baseband processing is for FEC decoding [1], [2], which equals to 10–100 GOPs/s within
  • 2) Logic Sharing Results: The silicon area reduction through trellis application specified instruction-set processor (TASIP) hardware sharing is discussed in the following
  • The data path and memory modules are shared by the decoding algorithms which leads to an area and memory bandwidth saving
  • The proposed TASIP is evaluated with other trimode state-of-the-art decoders which reveals its high decoding efficiency
Results
  • SYNTHESIS RESULTS AND COMPARISON

    The proposed design is synthesized by Synopsys Design Compiler, placed and routed by Cadence Encounter.
  • The total power consumption is 322 mW with the clock frequency of 200 MHz. The authors first discuss on the saving of memory cost, 3GPP-LTE Turbo, 802.11n LDPC, 802.16e LDPC, and 802.11 CC are separately implemented to compare the resource consumption with this TASIP solution.
  • There are some modules shared, additional multiplexing routes are needed for the memory sharing and datapath sharing
  • In another aspect, it reveals an obvious register resources saving through the unified architecture.
Conclusion
  • A trellis processor architecture supporting high-throughput multistandard turbo, QC-LDPC, and

    CC decoding is proposed.
  • A trellis processor architecture supporting high-throughput multistandard turbo, QC-LDPC, and.
  • CC decoding is proposed.
  • The decoding algorithm similarities are investigated and a parallel FBR decoding routine along with a code segmentation method is given.
  • Under the FBR characteristics, a unified SIMD architecture is proposed supporting FR and BR simultaneously processing.
  • The data path and memory modules are shared by the decoding algorithms which leads to an area and memory bandwidth saving.
  • The proposed TASIP is evaluated with other trimode state-of-the-art decoders which reveals its high decoding efficiency
Tables
  • Table1: FBR CONTROLLING KEY SIGNALS
  • Table2: LOGIC SHARING IN TERMS OF μm2 part of the core with the same distance to the permutation network. ATU routes in relatively less density to avoid routing congestion
  • Table3: FEC INSTRUCTIONS
  • Table4: SUMMATION OF MEMORY BANDWIDTH (BITS/CYCLE)
  • Table5: COMPARISON WITH STATE-OF-THE-ART MULTIMODE FEC DECODERS
  • Table6: MEMORY SHARING RESULTS IN TERMS OF BITS
Download tables as Excel
Funding
  • This work was supported by the National High-Tech Research and Development Program (863 Program) of China under Grant 2014AA01A705. (Corresponding author: Dake Liu.)
Reference
  • C. H. van Berkel, “Multi-core for mobile phones,” in Proc. Design, Autom. Test Eur. Conf. Exhibit. (DATE), Apr. 2009, pp. 1260–1265.
    Google ScholarLocate open access versionFindings
  • Y. Lin et al., “SODA: A low-power architecture for software radio,” in Proc. 33rd Annu. Int. Symp. Comput. Archit. (ISCA), 2006, pp. 89–101.
    Google ScholarLocate open access versionFindings
  • J. Dielissen, N. Engin, S. Sawitzki, and K. van Berkel, “Multistandard FEC decoders for wireless devices,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 55, no. 3, pp. 284–288, Mar. 2008.
    Google ScholarLocate open access versionFindings
  • D. Liu, Embedded DSP Processor Design: Application Specific Instruction Set Processors, vol.
    Google ScholarLocate open access versionFindings
  • 2. San Mateo, CA, USA: Morgan Kaufmann, 2008.
    Google ScholarFindings
  • [5] T. Vogt and N. Wehn, “A reconfigurable ASIP for convolutional and turbo decoding in an SDR environment,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 16, no. 10, pp. 1309–1320, Oct. 2008.
    Google ScholarLocate open access versionFindings
  • [6] M. Alles, T. Vogt, and N. Wehn, “FlexiChaP: A reconfigurable ASIP Symp. Turbo Codes Rel. Topics, Sep. 2008, pp. 84–89.
    Google ScholarLocate open access versionFindings
  • [7] C. Brehm, T. Ilnseher, and N. Wehn, “A scalable multi-ASIP architecture for standard compliant trellis decoding,” in Proc. Int. SoC Design Conf. (ISOCC), Nov. 2011, pp. 349–352.
    Google ScholarLocate open access versionFindings
  • [8] F. Naessens et al., “A unified instruction set programmable architecture for multi-standard advanced forward error correction,” in Proc. IEEE Workshop Signal Process. Syst. (SiPS), Oct. 2008, pp. 31–36.
    Google ScholarLocate open access versionFindings
  • Decoding. [Online]. Available: http://www.design-reuse.
    Findings
  • [10] P. Murugappa, R. Al-Khayat, A. Baghdadi, and M. Jezequel, “A flexible high throughput multi-ASIP architecture for LDPC and turbo decoding,” in Proc. Design, Autom. Test Eur. Conf. Exhibit. (DATE), Mar. 2011, pp. 1–6.
    Google ScholarLocate open access versionFindings
  • [11] S. Kunze, E. Matus, G. Fettweis, and T. Kobori, “Combining LDPC, turbo and Viterbi decoders: Benefits and costs,” in Proc. IEEE Workshop Signal Process. Syst. (SiPS), Oct. 2011, pp. 216–221.
    Google ScholarLocate open access versionFindings
  • [12] A. Niktash, H. T. Parizi, A. H. Kamalizad, and N. Bagherzadeh, “RECFEC: A reconfigurable FEC processor for Viterbi, turbo, Reed–Solomon and LDPC coding,” in Proc. IEEE Wireless Commun. Netw. Conf. (WCNC), Apr. 2008, pp. 605–610.
    Google ScholarLocate open access versionFindings
  • [13] L. Bahl, J. Cocke, F. Jelinek, and J. Raviv, “Optimal decoding of linear codes for minimizing symbol error rate (Corresp.),” IEEE Trans. Inf. Theory, vol. 20, no. 2, pp. 284–287, Mar. 1974.
    Google ScholarLocate open access versionFindings
  • [14] M. M. Mansour, “A turbo-decoding message-passing algorithm for sparse parity-check matrix codes,” IEEE Trans. Signal Process., vol. 54, no. 11, pp. 4376–4392, Nov. 2006.
    Google ScholarLocate open access versionFindings
  • [15] Y. Sun and J. R. Cavallaro, “A low-power 1-Gbps reconfigurable LDPC SOC Conf., Sep. 2008, pp. 367–370.
    Google ScholarLocate open access versionFindings
  • [16] J. Chen, A. Dholakia, E. Eleftheriou, M. P. C. Fossorier, and X.-Y. Hu, “Reduced-complexity decoding of LDPC codes,” IEEE Trans. Commun., vol. 53, no. 8, pp. 1288–1299, Aug. 2005.
    Google ScholarLocate open access versionFindings
  • [17] Y. Sun and J. R. Cavallaro, “Unified decoder architecture for Syst. (SiPS), Oct. 2008, pp. 13–18.
    Google ScholarFindings
  • [18] G. Gentile, M. Rovini, and L. Fanucci, “A multi-standard flexible turbo/LDPC decoder via ASIC design,” in Proc. 6th Int. Symp. Turbo Codes Iterative Inf. Process. (ISTC), Sep. 2010, pp. 294–298.
    Google ScholarLocate open access versionFindings
  • [19] J. Dion, M. Hamon, P. Penard, M. Arzel, and M. Jezequel, “Multistandard trellis-based FEC decoder,” in Proc. Conf. Design Archit. Signal Image Process. (DASIP), Oct. 2012, pp. 1–7.
    Google ScholarLocate open access versionFindings
  • [20] M. A. Bickerstaff et al., “A unified turbo/Viterbi channel decoder for GPP mobile wireless in 0.18-μm CMOS,” IEEE J. Solid-State Circuits, vol. 37, no. 11, pp. 1555–1564, Nov. 2002.
    Google ScholarLocate open access versionFindings
  • [21] M. K. Kunchamwar, D. P. Prasad, P. Hegde, P. T. Balsara, and Process. Workshops (ICPPW), Sep. 2010, pp. 34–43.
    Google ScholarFindings
  • [22] S. Lin and D. J. Costello, Error Control Coding, 2nd ed. Upper Saddle River, NJ, USA: Prentice-Hall, 2004.
    Google ScholarFindings
  • [23] Y. Sun, J. R. Cavallaro, and T. Ly, “Scalable and low power LDPC Int. SoCC, Sep. 2009, pp. 267–270.
    Google ScholarLocate open access versionFindings
  • [24] D. Wu, R. Asghar, Y. Huang, and D. Liu, “Implementation of a highspeed parallel turbo decoder for 3GPP LTE terminals,” in Proc. IEEE 8th Int. Conf. ASIC (ASICON), Oct. 2009, pp. 481–484.
    Google ScholarLocate open access versionFindings
  • [25] R. Asghar, D. Wu, A. Saeed, Y. Huang, and D. Liu, “Implementation of a radix-4, parallel turbo decoder and enabling the multi-standard support,” J. Signal Process. Syst., vol. 66, no. 1, pp. 25–41, Jan. 2012.
    Google ScholarLocate open access versionFindings
  • [26] C.-C. Wong, Y.-Y. Lee, and H.-C. Chang, “A 188-size 2.1 mm2 reconfigurable turbo decoder chip with parallel architecture for 3GPP LTE system,” in Proc. Symp. VLSI Circuits, Jun. 2009, pp. 288–289.
    Google ScholarLocate open access versionFindings
  • [27] W. Sulek, “On the overflow problem in finite precision turbo decoding message passing,” IEEE Trans. Commun., vol. 60, no. 5, pp. 1253–1259, May 2012.
    Google ScholarLocate open access versionFindings
  • [28] A. H. Sani, P. Coussy, and C. Chavet, “A first step toward on-chip memory mapping for parallel turbo and LDPC decoders: A polynomial time mapping algorithm,” IEEE Trans. Signal Process., vol. 61, no. 16, pp. 4127–4140, Aug. 2013.
    Google ScholarLocate open access versionFindings
  • [29] A. Tarable, S. Benedetto, and G. Montorsi, “Mapping interleaving laws to parallel turbo and LDPC decoder architectures,” IEEE Trans. Inf. Theory, vol. 50, no. 9, pp. 2002–2009, Sep. 2004.
    Google ScholarLocate open access versionFindings
  • [30] C. Condo, M. Martina, and G. Masera, “VLSI implementation of a multi-mode turbo/LDPC decoder architecture,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 60-I, no. 6, pp. 1441–1454, Jun. 2013. [Online]. Available: http://dx.doi.org/10.1109/TCSI.2012.2221216 Dake Liu (SM’08) received the D.Tech. degree from Linköping University, Linköping, Sweden, in 1995.
    Locate open access versionFindings
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