Median Filter Architecture by Accumulative Parallel Counters

Circuits and Systems II: Express Briefs, IEEE Transactions  (2015)

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摘要
The time to process each of W/B processing blocks of a median calculation method on a set of N W-bit integers is improved here by a factor of three compared to the literature. Parallelism uncovered in blocks containing B-bit slices are exploited by independent accumulative parallel counters so that the median is calculated faster than any known previous method for any N, W values. The improvements to the method are discussed in the context of calculating the median for a moving set of N integers for which a pipelined architecture is developed. An extra benefit of smaller area for the architecture is also reported.
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关键词
image processing,median filter,pipelined processing,decoding,vectors,parallel processing,radiation detectors,hardware,registers,computer architecture
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