A Fast Locking-in and Low Jitter PLLWith a Process-Immune Locking-in Monitor

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, Volume 22, Issue 10, 2014, Pages 2216-2220.

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摘要

In this brief, a digital-control adaptive phase-locked loop (PLL) with a digital locking-in monitor (LIM) consisting of a time-to-digital converter (TDC) and a bandwidth control unit (BCU) is proposed to reduce the locking time as well as to suppress the jitter when locked. It uses a delay-independent threshold in a dual-slope transfer fu...更多

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