A Test Pattern Selection Method for Dynamic Burn-in of Logic Circuits Based on ATPG Technique

State transition of nodes in the circuit generates heat which usually needs to be minimized for reliability consideration. In this work, instead, the heat generated is used to burn-in the CUT. A burn-in test pattern selection technique based on the ATPG approach for maximizing the dynamic power of the CUT is proposed. Experimental results show that the technique is effective in selecting the patterns which offer maximal power. It can be applied into the burn-in of logic circuits and SoCs in an energy saving manner.