A Test Pattern Selection Method for Dynamic Burn-in of Logic Circuits Based on ATPG Technique

2013 IEEE 10TH INTERNATIONAL CONFERENCE ON ASIC (ASICON), (2013)

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Abstract:

State transition of nodes in the circuit generates heat which usually needs to be minimized for reliability consideration. In this work, instead, the heat generated is used to burn-in the CUT. A burn-in test pattern selection technique based on the ATPG approach for maximizing the dynamic power of the CUT is proposed. Experimental results...More

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