Processor Design with Asymmetric Reliability

ISVLSI, pp. 565-570, 2014.

被引用12|浏览3
EI WOS

摘要

Continuous shrinking of device size has introduced reliability as a new design challenge for embedded processors. Error mitigation techniques trade off reliability for other design metrics such as performance and power consumption. State-of-the-art fault-tolerant designs involve cross-layer error management, which lead to an over-protecte...更多

代码

数据

ZH
24小时获取PDF
引用
您的评分 :
0

 

标签
评论