Modeling of resistance in FinFET local interconnect
Circuits and Systems I: Regular Papers, IEEE Transactions（2015）
摘要
We present an innovative and comprehensive approach to model the resistance of local interconnect used in finFET technologies. Our parasitic resistance formulas for finFET source/drain regions cover both merged and unmerged fin processes. They have been verified with field solver simulation results, and are found to be accurate over a wide range of parameter values. Our local interconnect resistance model has been used in 14nm finFET technology, and is a critical part of compact models used in both extraction flow and schematic/pre-layout flow.
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关键词
finfet local interconnect,semiconductor device models,resistance modeling,integrated circuit interconnections,source-drain regions,parasitic resistance,field solver simulation,parasitic resistance formulas,compact models,schematic-pre-layout flow,source/drain resistance,unmerged fin process,size 14 nm,schematic model,local interconnect,integrated circuit layout,mosfet,finfet,FinFET
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